Why I use scripting?
posted on March 01, 2020
Using an RP2040 for programming and debugging the CP SOM ONE
posted on November 25, 2023
My FPGA development environment
posted on September 16, 2023
The FPGA invasion
posted on January 02, 2023
How to find documentation about DSP and FPGA.
posted on July 30, 2022
posted on January 03, 2022
Remote debugging via hardware server.
posted on November 08, 2021
Designing an FPGA board.
posted on September 30, 2020
Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.
posted on November 11, 2023
Designing an FPGA SOM.
posted on October 28, 2023
Getting started with a Zynq development board. Base PS Design.
posted on October 14, 2023
Custom HW design for Red Pitaya STEMlab
posted on September 30, 2023
Getting started with Red Pitaya STEMlab
posted on September 02, 2023
The Gate Array News 2023.
posted on July 29, 2023
Developing a SYZYGY peripheral
posted on June 17, 2023
DMA, Petalinux and the ZUBoard-1CG
posted on June 04, 2023
Working with Kria SOM.
posted on May 07, 2023
Configuring the PL design from the PS on Zynq MPSOC.
posted on April 08, 2023
Vitis acceleration flow and the KR260.
posted on February 27, 2023
Adding a MicroBlaze coprocessor to an edge computer.
posted on January 30, 2023
Implementing QAM16 on FPGA.
posted on December 05, 2022
Running Petalinux on a Microblaze soft core.
posted on February 14, 2022
Implementing high order filters with FIR Compiler.
posted on October 25, 2021
FFT algorithm using an FPGA and XDMA.
posted on October 11, 2021
Implementing a dual core processor in FPGA.
posted on September 13, 2021
Using PCIe in Xilinx 7 Series.
posted on August 30, 2021
Adding windows to xFFT IP.
posted on May 31, 2021
Managing AXI4-Stream from MATLAB.
posted on April 05, 2021
Development boards I use.
posted on March 22, 2021
Using IIO to manage an ADC from Petalinux.
posted on March 08, 2021
Connecting an SSD to Zynq MPSOC.
posted on February 22, 2021
Using FPGA Data Capture to debug a design.
posted on January 25, 2021
Using DSP48E1 Slice.
posted on January 11, 2021
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)
posted on December 28, 2020
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)
posted on December 21, 2020
Increasing ADC resolution using oversampling.
posted on November 23, 2020
Using Xilinx’s FIR Compiler.
posted on November 09, 2020
Creating an AXI Stream IP for an acquisition system.
posted on October 26, 2020
Using the DMA and AXI4 Stream on Zynq US+.
posted on October 12, 2020
Asymmetric multiprocessing on Zynq MPSOC.
posted on September 01, 2020
Custom AXI IP for acceleration.
posted on July 24, 2020
Single tone detector with Genesys ZU and RTU.
posted on July 06, 2020
Eclypse Z7 and xFFT.
posted on May 25, 2020
Eclypse Z7, ZMODs and SYZYGY.
posted on May 03, 2020
Emulating hardware with Zynq.
posted on April 26, 2020
Real time filter compute with PYNQ
posted on March 31, 2020
posted on March 21, 2020
Designing IIR filters in Python.
posted on July 15, 2023
Implementing a Buck converter in RTL.
posted on July 01, 2023
Simulating DSP algorithms using Verilog.
posted on May 20, 2023
A different approach to the discrete Fourier transform.
posted on October 24, 2022
True RMS compute in FPGA.
posted on July 18, 2022
Division algorithms in FPGA.
posted on June 20, 2022
Frequency warping using the bilinear transform.
posted on May 09, 2022
Exploring the Cordic algorithm.
posted on April 25, 2022
posted on April 11, 2022
Proportional – Integral regulator. Implementation and verification.
posted on March 14, 2022
Digital control loops. Theoretical approach.
posted on February 28, 2022
Downsampling using MATLAB and the Microchip's Icicle kit.
Ripple suppression circuit for PWM DAC.
posted on January 31, 2022
Single pole filter without multiplications.
posted on November 22, 2021
Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7
posted on November 15, 2021
Equalizing IIR filters for a constant group delay.
posted on July 12, 2021
Audio equalizer based on FIR filters.
posted on June 28, 2021
Implementing a FIR filter using folding.
posted on May 17, 2021
Implementing a digital biquad filter in Verilog.
posted on April 19, 2021
Using moving average filters for hard filtering.
EclypseZ7, Petalinux and signal processing at the edge.
posted on June 08, 2020
Creating Pynq images for custom boards.
posted on July 26, 2021
Using HDL Coder WFA to implement a distortion effect.
posted on February 08, 2021
Using the Python API for USRP SDR devices.
posted on December 19, 2022
Trying to hack a garage door opener with the USRP B210.
posted on September 12, 2022
F4PGA and Project XRAY.
posted on August 29, 2022
Adding the Digilent USB104 A7 board to Litex.
posted on July 04, 2022
How to use a digital oscilloscope.
Running Linux on a Litex SoC.
posted on March 28, 2022
Building a SoC with Litex.
posted on January 17, 2022
Discovering SDR with GNU Radio and USRP B205Mini.
posted on December 08, 2020
Genesys ZU and Zynq US+.
posted on June 29, 2020
Running Ubuntu in the Microchip's Icicle Kit.
posted on March 26, 2023
Creating a custom PolarFire SoC design.
posted on October 10, 2022
Debugging a Microchip's SmartFusion2 SoC.
posted on September 26, 2022
Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.
posted on December 20, 2021
Controlling a SMPS from MSS with SmartFusion2 SoC.
posted on September 27, 2021
Creating a RISC-V based design on SmartFusion®2 SoC.
posted on June 14, 2021
Discovering the SmartFusion® 2 SoC.
posted on May 03, 2021
Capturing the ISM band with RTL SDR.
posted on April 23, 2023
Designing a FM receiver with the USRP B205mini #WorldRadioDay22.
posted on February 13, 2022
Running a physical model on a Speedgoat.
posted on February 13, 2023
Getting started with Speedgoat.
posted on January 16, 2023
Discovering Gowin FPGA.
posted on December 06, 2021
Writing Verilog code using Python with Migen.
posted on November 07, 2022
Implementing FPGA designs in the cloud
posted on November 21, 2022
posted on March 12, 2023