tcl
workflow
Using an RP2040 for programming and debugging the CP SOM ONE
My FPGA development environment
How to find documentation about DSP and FPGA.
Remote debugging via hardware server.
xilinx
Running subcycle average models on Speedgoat Performance System (II).
Connecting an FPGA accelerator to the Raspberry Pi 5
Running subcycle average models on Speedgoat Performance System (I).
Getting started with ZuBoard and Petalinux
Using an RP2040 for programming and debugging the CP SOM ONE
Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.
Getting started with a Zynq development board. Base PS Design.
Custom HW design for Red Pitaya STEMlab
Getting started with Red Pitaya STEMlab
Developing a SYZYGY peripheral
DMA, Petalinux and the ZUBoard-1CG
Configuring the PL design from the PS on Zynq MPSOC.
Vitis acceleration flow and the KR260.
Adding a MicroBlaze coprocessor to an edge computer.
Running Petalinux on a Microblaze soft core.
Remote debugging via hardware server.
Implementing high order filters with FIR Compiler.
FFT algorithm using an FPGA and XDMA.
Implementing a dual core processor in FPGA.
Using PCIe in Xilinx 7 Series.
Managing AXI4-Stream from MATLAB.
Using IIO to manage an ADC from Petalinux.
Connecting an SSD to Zynq MPSOC.
Using FPGA Data Capture to debug a design.
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)
Increasing ADC resolution using oversampling.
Creating an AXI Stream IP for an acquisition system.
Using the DMA and AXI4 Stream on Zynq US+.
Asymmetric multiprocessing on Zynq MPSOC.
Custom AXI IP for acceleration.
Single tone detector with Genesys ZU and RTU.
Real time filter compute with PYNQ
dsp
Implementing and ADC inside the FPGA
Solving a Boost converter in FPGA
Implementing a DC remover filter on FPGA
Designing IIR filters in Python.
Implementing a Buck converter in RTL.
Developing a SYZYGY peripheral
Simulating DSP algorithms using Verilog.
A different approach to the discrete Fourier transform.
Frequency warping using the bilinear transform.
Exploring the Cordic algorithm.
Proportional – Integral regulator. Implementation and verification.
Digital control loops. Theoretical approach.
Downsampling using MATLAB and the Microchip's Icicle kit.
Ripple suppression circuit for PWM DAC.
Single pole filter without multiplications.
Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7
Implementing high order filters with FIR Compiler.
FFT algorithm using an FPGA and XDMA.
Equalizing IIR filters for a constant group delay.
Audio equalizer based on FIR filters.
Implementing a FIR filter using folding.
Implementing a digital biquad filter in Verilog.
Using FPGA Data Capture to debug a design.
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)
Increasing ADC resolution using oversampling.
Creating an AXI Stream IP for an acquisition system.
Using the DMA and AXI4 Stream on Zynq US+.
Using moving average filters for hard filtering.
Single tone detector with Genesys ZU and RTU.
EclypseZ7, Petalinux and signal processing at the edge.
Real time filter compute with PYNQ
pynq
Designing IIR filters in Python.
Creating Pynq images for custom boards.
Real time filter compute with PYNQ
zynq
Running Petalinux 2023.2 on the KD240
Getting started with ZuBoard and Petalinux
Getting started with a Zynq development board. Base PS Design.
Custom HW design for Red Pitaya STEMlab
Getting started with Red Pitaya STEMlab
Implementing a Buck converter in RTL.
Configuring the PL design from the PS on Zynq MPSOC.
Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7
Using PCIe in Xilinx 7 Series.
Creating Pynq images for custom boards.
Using IIO to manage an ADC from Petalinux.
Connecting an SSD to Zynq MPSOC.
Using HDL Coder WFA to implement a distortion effect.
Creating an AXI Stream IP for an acquisition system.
Using the DMA and AXI4 Stream on Zynq US+.
Asymmetric multiprocessing on Zynq MPSOC.
Custom AXI IP for acceleration.
Single tone detector with Genesys ZU and RTU.
EclypseZ7, Petalinux and signal processing at the edge.
digilent
Using the Python API for USRP SDR devices.
Trying to hack a garage door opener with the USRP B210.
Adding the Digilent USB104 A7 board to Litex.
How to use a digital oscilloscope.
Frequency warping using the bilinear transform.
Running Petalinux on a Microblaze soft core.
Equalizing IIR filters for a constant group delay.
Discovering SDR with GNU Radio and USRP B205Mini.
EclypseZ7, Petalinux and signal processing at the edge.
zynq_us
filters
Implementing and ADC inside the FPGA
Solving a Boost converter in FPGA
Implementing a DC remover filter on FPGA
Simulating DSP algorithms using Verilog.
Audio equalizer based on FIR filters.
Implementing a FIR filter using folding.
Implementing a digital biquad filter in Verilog.
Managing AXI4-Stream from MATLAB.
Using moving average filters for hard filtering.
Single tone detector with Genesys ZU and RTU.
acceleration
Running Petalinux 2023.2 on the KD240
Connecting an FPGA accelerator to the Raspberry Pi 5
Vitis acceleration flow and the KR260.
Adding a MicroBlaze coprocessor to an edge computer.
FFT algorithm using an FPGA and XDMA.
Custom AXI IP for acceleration.
microchip
Running Ubuntu in the Microchip's Icicle Kit.
Creating a custom PolarFire SoC design.
Debugging a Microchip's SmartFusion2 SoC.
Downsampling using MATLAB and the Microchip's Icicle kit.
Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.
Controlling a SMPS from MSS with SmartFusion2 SoC.
Creating a RISC-V based design on SmartFusion®2 SoC.
Discovering the SmartFusion® 2 SoC.
Increasing ADC resolution using oversampling.
sdr
Simulating DSP algorithms using Verilog.
Capturing the ISM band with RTL SDR.
Using the Python API for USRP SDR devices.
Trying to hack a garage door opener with the USRP B210.
Designing a FM receiver with the USRP B205mini #WorldRadioDay22.
Discovering SDR with GNU Radio and USRP B205Mini.
audio
Using HDL Coder WFA to implement a distortion effect.
Discovering SDR with GNU Radio and USRP B205Mini.
hdl coder
Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7
Managing AXI4-Stream from MATLAB.
Using HDL Coder WFA to implement a distortion effect.
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)
Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)
matlab
Running subcycle average models on Speedgoat Performance System (II).
Running subcycle average models on Speedgoat Performance System (I).
Implementing a DC remover filter on FPGA
Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.
Implementing a Buck converter in RTL.
Running a physical model on a Speedgoat.
Getting started with Speedgoat.
Digital control loops. Theoretical approach.
Using FPGA Data Capture to debug a design.
smartfusion 2 soc
Debugging a Microchip's SmartFusion2 SoC.
Controlling a SMPS from MSS with SmartFusion2 SoC.
Creating a RISC-V based design on SmartFusion®2 SoC.
Discovering the SmartFusion® 2 SoC.
microblaze
Implementing a dual core processor in FPGA.
gowin
polarfire soc
Running Ubuntu in the Microchip's Icicle Kit.
Creating a custom PolarFire SoC design.
Downsampling using MATLAB and the Microchip's Icicle kit.
Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.
litex
Writing Verilog code using Python with Migen.
Adding the Digilent USB104 A7 board to Litex.
linux
Connecting an FPGA accelerator to the Raspberry Pi 5
Getting started with the RP2040 PMOD
Running Ubuntu in the Microchip's Icicle Kit.
Running Petalinux on a Microblaze soft core.
tools
Getting started with the RP2040 PMOD
Using an RP2040 for programming and debugging the CP SOM ONE
Custom HW design for Red Pitaya STEMlab
My FPGA development environment
Getting started with Red Pitaya STEMlab
Developing a SYZYGY peripheral
Implementing FPGA designs in the cloud
Writing Verilog code using Python with Migen.
How to use a digital oscilloscope.
f4pga
usrp
Capturing the ISM band with RTL SDR.
Trying to hack a garage door opener with the USRP B210.
speedgoat
Running subcycle average models on Speedgoat Performance System (II).
Running subcycle average models on Speedgoat Performance System (I).
Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.
Running a physical model on a Speedgoat.
Getting started with Speedgoat.
petalinux
DMA, Petalinux and the ZUBoard-1CG
Configuring the PL design from the PS on Zynq MPSOC.
Vitis acceleration flow and the KR260.
kria
Running Petalinux 2023.2 on the KD240
Vitis acceleration flow and the KR260.
workspace
trenz
Configuring the PL design from the PS on Zynq MPSOC.
python
Designing IIR filters in Python.
fpga
Getting Started with Zynq
Getting started with ZuBoard and Petalinux
Getting started with a Zynq development board. Base PS Design.
devices
Getting started with the RP2040 PMOD
ohsim
Implementing and ADC inside the FPGA
Solving a Boost converter in FPGA