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tcl

Creating a custom AXI IP. The professional way.

Why I use scripting?



workflow

Using an RP2040 for programming and debugging the CP SOM ONE

My FPGA development environment

The FPGA invasion

How to find documentation about DSP and FPGA.

Why FPGA?

Remote debugging via hardware server.

Designing an FPGA board.

Why I use scripting?



xilinx

Using PS clocks for your PL designs

Creating a custom AXI IP. The professional way.

Running subcycle average models on Speedgoat Performance System (II).

Connecting an FPGA accelerator to the Raspberry Pi 5

Running subcycle average models on Speedgoat Performance System (I).

Getting started with ZuBoard and Petalinux

The art of sharing

Using an RP2040 for programming and debugging the CP SOM ONE

Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.

Designing an FPGA SOM.

Getting started with a Zynq development board. Base PS Design.

Custom HW design for Red Pitaya STEMlab

Getting started with Red Pitaya STEMlab

The Gate Array News 2023.

Developing a SYZYGY peripheral

DMA, Petalinux and the ZUBoard-1CG

Working with Kria SOM.

Configuring the PL design from the PS on Zynq MPSOC.

Vitis acceleration flow and the KR260.

Adding a MicroBlaze coprocessor to an edge computer.

Implementing QAM16 on FPGA.

Running Petalinux on a Microblaze soft core.

Remote debugging via hardware server.

Implementing high order filters with FIR Compiler.

FFT algorithm using an FPGA and XDMA.

Implementing a dual core processor in FPGA.

Using PCIe in Xilinx 7 Series.

Adding windows to xFFT IP.

Managing AXI4-Stream from MATLAB.

Development boards I use.

Using IIO to manage an ADC from Petalinux.

Connecting an SSD to Zynq MPSOC.

Using FPGA Data Capture to debug a design.

Using DSP48E1 Slice.

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)

Increasing ADC resolution using oversampling.

Using Xilinx’s FIR Compiler.

Creating an AXI Stream IP for an acquisition system.

Using the DMA and AXI4 Stream on Zynq US+.

Designing an FPGA board.

Asymmetric multiprocessing on Zynq MPSOC.

Custom AXI IP for acceleration.

Single tone detector with Genesys ZU and RTU.

Eclypse Z7 and xFFT.

Eclypse Z7, ZMODs and SYZYGY.

Emulating hardware with Zynq.

Real time filter compute with PYNQ

DDR Resources



dsp

Undersampling. Playing with Nyquist and Shannon.

Implementing and ADC inside the FPGA

Solving a Boost converter in FPGA

The art of sharing

Implementing a DC remover filter on FPGA

Designing IIR filters in Python.

Implementing a Buck converter in RTL.

Developing a SYZYGY peripheral

Simulating DSP algorithms using Verilog.

A different approach to the discrete Fourier transform.

True RMS compute in FPGA.

Division algorithms in FPGA.

Frequency warping using the bilinear transform.

Exploring the Cordic algorithm.

FilterBuilder v0.1

Proportional – Integral regulator. Implementation and verification.

Digital control loops. Theoretical approach.

Downsampling using MATLAB and the Microchip's Icicle kit.

Ripple suppression circuit for PWM DAC.

Single pole filter without multiplications.

Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7

Implementing high order filters with FIR Compiler.

FFT algorithm using an FPGA and XDMA.

Equalizing IIR filters for a constant group delay.

Audio equalizer based on FIR filters.

Adding windows to xFFT IP.

Implementing a FIR filter using folding.

Implementing a digital biquad filter in Verilog.

Using FPGA Data Capture to debug a design.

Using DSP48E1 Slice.

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)

Increasing ADC resolution using oversampling.

Using Xilinx’s FIR Compiler.

Creating an AXI Stream IP for an acquisition system.

Using the DMA and AXI4 Stream on Zynq US+.

Using moving average filters for hard filtering.

Single tone detector with Genesys ZU and RTU.

EclypseZ7, Petalinux and signal processing at the edge.

Eclypse Z7 and xFFT.

Real time filter compute with PYNQ



pynq

Using PS clocks for your PL designs

Designing IIR filters in Python.

Creating Pynq images for custom boards.

Emulating hardware with Zynq.

Real time filter compute with PYNQ



zynq

Using PS clocks for your PL designs

Creating a custom AXI IP. The professional way.

BLDC motor control with the KD240

Running Petalinux 2023.2 on the KD240

Getting started with ZuBoard and Petalinux

The art of sharing

Getting started with a Zynq development board. Base PS Design.

Custom HW design for Red Pitaya STEMlab

Getting started with Red Pitaya STEMlab

The Gate Array News 2023.

Implementing a Buck converter in RTL.

Configuring the PL design from the PS on Zynq MPSOC.

Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7

Using PCIe in Xilinx 7 Series.

Creating Pynq images for custom boards.

Using IIO to manage an ADC from Petalinux.

Connecting an SSD to Zynq MPSOC.

Using HDL Coder WFA to implement a distortion effect.

Creating an AXI Stream IP for an acquisition system.

Using the DMA and AXI4 Stream on Zynq US+.

Asymmetric multiprocessing on Zynq MPSOC.

Custom AXI IP for acceleration.

Single tone detector with Genesys ZU and RTU.

EclypseZ7, Petalinux and signal processing at the edge.

Eclypse Z7, ZMODs and SYZYGY.

Emulating hardware with Zynq.



digilent

Using the Python API for USRP SDR devices.

Implementing QAM16 on FPGA.

Trying to hack a garage door opener with the USRP B210.

F4PGA and Project XRAY.

Adding the Digilent USB104 A7 board to Litex.

How to use a digital oscilloscope.

Frequency warping using the bilinear transform.

Running Linux on a Litex SoC.

Running Petalinux on a Microblaze soft core.

Building a SoC with Litex.

Equalizing IIR filters for a constant group delay.

Discovering SDR with GNU Radio and USRP B205Mini.

Genesys ZU and Zynq US+.

EclypseZ7, Petalinux and signal processing at the edge.

Eclypse Z7 and xFFT.

Eclypse Z7, ZMODs and SYZYGY.



zynq_us

Genesys ZU and Zynq US+.



filters

Implementing and ADC inside the FPGA

Solving a Boost converter in FPGA

Implementing a DC remover filter on FPGA

Simulating DSP algorithms using Verilog.

Audio equalizer based on FIR filters.

Implementing a FIR filter using folding.

Implementing a digital biquad filter in Verilog.

Managing AXI4-Stream from MATLAB.

Using DSP48E1 Slice.

Using Xilinx’s FIR Compiler.

Using moving average filters for hard filtering.

Single tone detector with Genesys ZU and RTU.



acceleration

Running Petalinux 2023.2 on the KD240

Connecting an FPGA accelerator to the Raspberry Pi 5

Vitis acceleration flow and the KR260.

Adding a MicroBlaze coprocessor to an edge computer.

FFT algorithm using an FPGA and XDMA.

Custom AXI IP for acceleration.



microchip

Running Ubuntu in the Microchip's Icicle Kit.

Creating a custom PolarFire SoC design.

Debugging a Microchip's SmartFusion2 SoC.

Downsampling using MATLAB and the Microchip's Icicle kit.

Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.

Controlling a SMPS from MSS with SmartFusion2 SoC.

Creating a RISC-V based design on SmartFusion®2 SoC.

Discovering the SmartFusion® 2 SoC.

Development boards I use.

Increasing ADC resolution using oversampling.



sdr

Undersampling. Playing with Nyquist and Shannon.

Simulating DSP algorithms using Verilog.

Capturing the ISM band with RTL SDR.

Using the Python API for USRP SDR devices.

Trying to hack a garage door opener with the USRP B210.

Designing a FM receiver with the USRP B205mini #WorldRadioDay22.

Discovering SDR with GNU Radio and USRP B205Mini.



audio

F4PGA and Project XRAY.

Using HDL Coder WFA to implement a distortion effect.

Discovering SDR with GNU Radio and USRP B205Mini.



hdl coder

Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7

Managing AXI4-Stream from MATLAB.

Using HDL Coder WFA to implement a distortion effect.

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)



matlab

Undersampling. Playing with Nyquist and Shannon.

Running subcycle average models on Speedgoat Performance System (II).

Running subcycle average models on Speedgoat Performance System (I).

Implementing a DC remover filter on FPGA

Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.

Implementing a Buck converter in RTL.

Running a physical model on a Speedgoat.

Getting started with Speedgoat.

Implementing QAM16 on FPGA.

Digital control loops. Theoretical approach.

Using FPGA Data Capture to debug a design.



smartfusion 2 soc

Debugging a Microchip's SmartFusion2 SoC.

Controlling a SMPS from MSS with SmartFusion2 SoC.

Creating a RISC-V based design on SmartFusion®2 SoC.

Discovering the SmartFusion® 2 SoC.



microblaze

Implementing a dual core processor in FPGA.



gowin

Discovering Gowin FPGA.



polarfire soc

Running Ubuntu in the Microchip's Icicle Kit.

Creating a custom PolarFire SoC design.

Downsampling using MATLAB and the Microchip's Icicle kit.

Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.



litex

Writing Verilog code using Python with Migen.

Adding the Digilent USB104 A7 board to Litex.

Running Linux on a Litex SoC.

Building a SoC with Litex.



linux

Connecting an FPGA accelerator to the Raspberry Pi 5

Getting started with the RP2040 PMOD

Running Ubuntu in the Microchip's Icicle Kit.

Running Petalinux on a Microblaze soft core.



tools

Getting started with the RP2040 PMOD

Using an RP2040 for programming and debugging the CP SOM ONE

Designing an FPGA SOM.

Custom HW design for Red Pitaya STEMlab

My FPGA development environment

Getting started with Red Pitaya STEMlab

Developing a SYZYGY peripheral

Implementing FPGA designs in the cloud

Writing Verilog code using Python with Migen.

How to use a digital oscilloscope.

FilterBuilder v0.1



f4pga

F4PGA and Project XRAY.



usrp

Capturing the ISM band with RTL SDR.

Trying to hack a garage door opener with the USRP B210.



speedgoat

Running subcycle average models on Speedgoat Performance System (II).

Running subcycle average models on Speedgoat Performance System (I).

Data acquisition from an electric model running on the FPGA of a Speedgoat Performance.

Running a physical model on a Speedgoat.

Getting started with Speedgoat.



petalinux

DMA, Petalinux and the ZUBoard-1CG

Working with Kria SOM.

Configuring the PL design from the PS on Zynq MPSOC.

Vitis acceleration flow and the KR260.



kria

BLDC motor control with the KD240

Running Petalinux 2023.2 on the KD240

Working with Kria SOM.

Vitis acceleration flow and the KR260.



workspace

New blog.



trenz

Configuring the PL design from the PS on Zynq MPSOC.



python

Designing IIR filters in Python.



fpga

Designing an FPGA SOM.

The Gate Array News 2023.



Getting Started with Zynq

Getting started with ZuBoard and Petalinux

Getting started with a Zynq development board. Base PS Design.



devices

Getting started with the RP2040 PMOD



ohsim

Implementing and ADC inside the FPGA

Solving a Boost converter in FPGA