# Eclypse Z7, ZMODs and SYZYGY.

Few months ago, Digilent presented their new development platforms based in Zynq and Zynq US+, with connectors compatibles with SYZYGY standard. This standard is in the middle between PMOD and FMC, with the enormous advantage that can be soldered by makers, with a solder, and some patience.

## Eclypse Z7 hardware.

First of all, let’s see the hardware we have. The brain of the board is an XC7Z020, maybe the most popular SOC of Xilinx. The board also have 2 leds, 2 push buttons, ethernet, RAM, more leds, ….. but, the important, 2 SYZYGY connector. SYZYGY is a emergent standard that, as I said before, try to fill the gap between FMC and PMOD, offering up to 500MHz in the standard choose by Digilent, and 28 single-ended signals, including 8 differential signals. Also includes 2 differential clock lanes, and, like PMC, a configurable VIO.

When I saw for first time this standard, first that comes to my mind was medium/high speed ADC and DAC, and those are one of the purposes of this connectors. Configurable VIO is also a very interesting, since we can configure for each device we connect, the supply, and the interface voltage. This configuration has to be saved in the peripheral board inside a memory, or, like the ZMODs, inside an ATMEL microcontroller. This information is readed by the Platform MCU on the Eclypse Z7, and this MCU configure one PMIC per connector. This PMIC give the corresponding voltage to the device, and the corresponding FPGA bank. This way, both supply and interface levels are the correct.

## ZMOD peripherals.

Digilent, with the Eclypse Z7 board, also launched 2 ZMOD periperals, one with a 125Msps, 14 bits ADC AD9648, and one with a 125Msps, 14 bits DAC, AD9717. Each of those devices has a SPI bus for configuration, and in the case of DAC, one 14 bits bus for DDR data, and in the case of the ADC, the chip has 2 14 bits buses for each channel, but only one is connected to the Zynq, so, by configuration, we have to configure that the 2 channels will be read through only one data bus, in DDR mode.

The configuration has no other mystery than read datasheet and send the correct configuration registers, but, for me, work with DDR channels is pretty new. First of all, FPGA has to supply clock for 2 devices, single-ended for the DAC, and differential for the ADC. For do this you can read my post about DDR resources on the 7 series, because this is an example of clock forwarding, and according the output buffer we choose, we have a differential output, or single ended output. The code for the differential output is the next.

/* Clock forwarding for ADC. Differential clock */
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
.Q(clk50mhz_ddr), /* Output clock the the output buffer */
.C(clk50mhz), /* Input clock to the DDR primitive */
.CE(1'b1),
.D1(1'b0),
.D2(1'b1),
.R(rst),
.S(1'b0)
);

OBUFDS #(
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
.I(clk50mhz_ddr)
);

Then, we have to serve data to the ADC and DAC also with a DDR format, so all data pin has to pass through the DDR primitives for ensure minimum jitter.

/* Output data */
generate for(genvar i=0; i<=13; i=i+1)
IDDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("SYNC")
endgenerate