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Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)

If I say “a software for engineering”, most of you probably think on MATLAB. I don’t know if exist any engineering field which have not a package on MATLAB, and obviously, digital signal processing and FPGA design is not one of them. The package DSP System Toolbox will give us all the functions t...

Published by P.Trujillo on Dec 21, 2020

Discovering SDR with GNU Radio and USRP B205Mini.

This post will be different from what I usually write. In general, in my posts, I talk about low-level algorithms and FPGA implementations to do digital signal processing, but this time I will use software to configure an specific purpose board. The board I will use is the USRP B205 Mini, a board...

Published by P.Trujillo on Dec 8, 2020

Increasing ADC resolution using oversampling.

After a few post dedicated exclusively to the FPGA, on this post I going to talk about a technique that can help us to improve the ADC resolution. To study this technique, we will use as a example the ADC which is based the Digilent’s ZMOD ADC, the AD9648.

Published by P.Trujillo on Nov 23, 2020

Using Xilinx’s FIR Compiler.

When we need a FIR filter, in general, or at least in my case, we already have a FIR filter HDL, where we only need to change the filter order to the application needs, in most cases this configuration can be parametrized, and the second thing we have to do is compute, quantify and write this new...

Published by P.Trujillo on Nov 9, 2020

Creating an AXI Stream IP for an acquisition system.

On the last post, we talk about the using of DMA to send data between PL and PS on SOC or MPSOC devices. The example that I proposed, was a kind of FFT compute accelerator, where a signal stored on the DDR was sent to the PL, and here, an FFT was computed, then, the result of the FFT was sent aga...

Published by P.Trujillo on Oct 26, 2020

Using the DMA and AXI4 Stream on Zynq US+.

When we are working with a SOC or MPSOC, is very common the data interchange between the PL and the APU, or between the PL and the RPU. To do that, the Zynq platform gives us several interfaces between the PL and both APU and RPU aka PS. In case of Zynq MPSOC, these interfaces are described on th...

Published by P.Trujillo on Oct 12, 2020

Designing an FPGA board.

Few month ago, I decided to design my own FPGA development board. The main reason for that was simply learn to do it, because I have design a lot o boards for peripherals, PMODs, or other projects, but never one based on FPGA, and for me, route a BGA was a big challenge.

Published by P.Trujillo on Sep 30, 2020

Application notes

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization.

Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter it they are developing for an STM32, or TI DSP or, of course, en FPGA. Filtering is such important because the majority of the applications are connected to the real world, so they need to captur...