Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)

In the last post, we had designed a filter with filter designer tool from MATLAB. After verifying the filter on MATLAB and Simulink, we have to generate the HDL and verify the implementation using FPGA-in-the-Loop, and later, verify the filter on the real design.

Published by P.Trujillo on Dec 28, 2020

Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1)

If I say “a software for engineering”, most of you probably think on MATLAB. I don’t know if exist any engineering field which have not a package on MATLAB, and obviously, digital signal processing and FPGA design is not one of them. The package DSP System Toolbox will give us all the functions t...

Published by P.Trujillo on Dec 21, 2020

Discovering SDR with GNU Radio and USRP B205Mini.

This post will be different from what I usually write. In general, in my posts, I talk about low-level algorithms and FPGA implementations to do digital signal processing, but this time I will use software to configure an specific purpose board. The board I will use is the USRP B205 Mini, a board...

Published by P.Trujillo on Dec 8, 2020

Increasing ADC resolution using oversampling.

After a few post dedicated exclusively to the FPGA, on this post I going to talk about a technique that can help us to improve the ADC resolution. To study this technique, we will use as a example the ADC which is based the Digilent’s ZMOD ADC, the AD9648.

Published by P.Trujillo on Nov 23, 2020

Using Xilinx’s FIR Compiler.

When we need a FIR filter, in general, or at least in my case, we already have a FIR filter HDL, where we only need to change the filter order to the application needs, in most cases this configuration can be parametrized, and the second thing we have to do is compute, quantify and write this new...

Published by P.Trujillo on Nov 9, 2020

Creating an AXI Stream IP for an acquisition system.

On the last post, we talk about the using of DMA to send data between PL and PS on SOC or MPSOC devices. The example that I proposed, was a kind of FFT compute accelerator, where a signal stored on the DDR was sent to the PL, and here, an FFT was computed, then, the result of the FFT was sent aga...

Published by P.Trujillo on Oct 26, 2020

Using the DMA and AXI4 Stream on Zynq US+.

When we are working with a SOC or MPSOC, is very common the data interchange between the PL and the APU, or between the PL and the RPU. To do that, the Zynq platform gives us several interfaces between the PL and both APU and RPU aka PS. In case of Zynq MPSOC, these interfaces are described on th...

Published by P.Trujillo on Oct 12, 2020