controlpaths.com

Using PS clocks for your PL designs

Sometimes people who want to start in the FPGA world ask me for a recommendation of a development board to start with. My answer to this question is always a Zynq board for several reasons. First, maybe they are not interested now in using the PS of a Zynq, but if they still improving their skill...

Published by P.Trujillo on Jun 9, 2024

Undersampling. Playing with Nyquist and Shannon.

This week, Digilent released the Zmod SDR, a new ZMOD module with SYZYGY interface intended for SDR projects. The features of this new Zmod include 2 RX channels with 14-bit resolution and an analog bandwidth from just 35 kHz to 470 MHz. The very interesting part of this Zmod is that it features ...

Published by P.Trujillo on May 26, 2024

Creating a custom AXI IP. The professional way.

Since you are reading this blog, I am pretty sure that you have used an AMD IP in at least one of your designs. Also, if you wanted a so specific IP for a specific project, likely you have bought an IP from a third-party vendor. Creating an IP, using it in your design, and even selling that IP is...

Published by P.Trujillo on May 12, 2024

BLDC motor control with the KD240

In the last article, I generated a base project for the KD240 kit from AMD. This kit is based on the Kria K24 SOM, the smallest brother of the K26 SOMs used in the KR260 and KV260. Since this board was released I have been interested in it because, I am not 100% sure of this, it was the first boa...

Published by P.Trujillo on Apr 28, 2024

Running Petalinux 2023.2 on the KD240

Every year, AMD releases several versions of all its development environments. From Vibado to Petalinux, all the environments are updated and introduce several changes in the way we use them. In this article, we are going to generate a hardware project with the KD240, and then we will create a Li...

Published by P.Trujillo on Apr 14, 2024

Implementing and ADC inside the FPGA

In my job, and also in the blog, I used to work with hardware-in-the-loop (HIL) systems. These devices can simulate in real-time the behavior of different analog circuits, and allow us to design algorithms and electronic circuits to control those circuits and test them against that real-time simu...

Published by P.Trujillo on Mar 31, 2024

Running subcycle average models on Speedgoat Performance System (II).

In this post, we talked about the PWM signals, and how we can capture them to convert that discontinuous signal into a continuous signal. This process is called subcycle average. Now, how can we integrate the subcycle average in a power stage model? If we take the Buck converter model I used in o...

Published by P.Trujillo on Mar 17, 2024

Application Notes

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization.

Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter it they are developing for an STM32, or TI DSP or, of course, en FPGA. Filtering is such important because the majority of the applications are connected to the real world, so they need to captur...

[AN002] Running subcycle average models on Speedgoat Performance System.

Materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) are making our power electronics converters faster and faster. This means small inductors and capacitors that make, in most cases, the cost of the devices decrease. This also means that the control devices also have to be faster, and n...