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Real time filter compute with PYNQ

We are in front of our customers, we have our design fully tested in our lab, all analog and digital filters works perfectly, but, in the customer installations there are an unknonw noise source. In this case, we must recompute digital filters, and spend time re sintesizing and implementing. Ma...

Published by P.Trujillo on Mar 31, 2020

DDR Resources

When most of us hear DDR, the first think that comes to our mind is RAM memories, but DDR is related with the comunication protocol, not with the memory. DDR means Double (Dual), Data Rate. This, basically means that un 1 single clock cycle, 2 data will be sended for every line. In this post I ...

Published by P.Trujillo on Mar 21, 2020

Why I use scripting?

When I started with FPGA, like probably all of us, the first thing I did when I arrived at my job position was to start Vivado (or ISE), and start coding, and once the code was write, cross my fingers, and Generate Bitsream. If all works fine, after some minutes (or hours), we had my bitstream ...

Published by P.Trujillo on Mar 1, 2020

Application notes

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization.

Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter it they are developing for an STM32, or TI DSP or, of course, en FPGA. Filtering is such important because the majority of the applications are connected to the real world, so they need to captur...