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Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.

In these rare days when getting a development board with a new FPGA is increasingly difficult, a new board has come into my hands. The board is the Icicle Kit, a Single Board Computer (SBC) from Microchip Technology. It is based on their PolarFire® SoC FPGA, the latest device released by Microchi...

Published by P.Trujillo on Dec 20, 2021

Discovering Gowin FPGA.

A few weeks ago Dialog Semiconductor announced a new series of FPGAs named ForgeFPGA. The highlight of these new devices are not high processing power, the highest speed or the big they are, the main highlights of these devices are Low-Power and Low-Cost. This kind of announcement shows us the wa...

Published by P.Trujillo on Dec 6, 2021

Single pole filter without multiplications.

When I am working in a design for an FPGA, which involves the acquisition of any signal, I usually have to design a filter before using that signal in the control loop, or a protection. If the use of this signal is critical, like the mentioned before, I usually have to design a filter considering...

Published by P.Trujillo on Nov 22, 2021

Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7

If I say “software for engineering”, most of you probably think of MATLAB. I don’t know if there is any field in engineering which does not have a package in MATLAB, and digital signal processing and FPGA design are certainly not among them. The package Signal processing Toolbox will give us all ...

Published by P.Trujillo on Nov 15, 2021

Remote debugging via hardware server.

In my daily life, as with other FPGA developers, I have a laptop where I write the code, and I connect to a remote host to synthesize and implement the FPGA designs. This offers me many advantages. The most important one is that I don’t need a very powerful processor or a large amount of RAM, sin...

Published by P.Trujillo on Nov 8, 2021

Implementing high order filters with FIR Compiler.

Many times, in our designs we find a signal that our interest band of frequency is very close to the band that we need to reject. In this case, in general, the most efficient way to attenuate the unwanted signal is using a 4th or 6th order IIR filter. This method will work very well, however, as ...

Published by P.Trujillo on Oct 25, 2021

FFT algorithm using an FPGA and XDMA.

In this blog we talked (a little) about the xDMA IP from Xilinx, and how to send and receive data through PCI using an FPGA. On that occasion, we used the Picozed board with the FMC Carrier gen 2. This time the board used Litefury from RHS research. This board is the same as the ACORN CLE-215, an...

Published by P.Trujillo on Oct 11, 2021

Application notes

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization.

Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter it they are developing for an STM32, or TI DSP or, of course, en FPGA. Filtering is such important because the majority of the applications are connected to the real world, so they need to captur...

[AN002] Running subcycle average models on Speedgoat Performance System.

Materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) are making our power electronics converters faster and faster. This means small inductors and capacitors that make, in most cases, the cost of the devices decrease. This also means that the control devices also have to be faster, and n...