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Why I use scripting?

When I started with FPGA, like probably all of us, the first thing I did when I arrived at my job position was to start Vivado (or ISE), and start coding, and once the code was write, cross my fingers, and Generate Bitsream. If all works fine, after some minutes (or hours), we had my bitstream ...


Published by P.Trujillo on Mar 1, 2020


Application notes

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization.

Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter it they are developing for an STM32, or TI DSP or, of course, en FPGA. Filtering is such important because the majority of the applications are connected to the real world, so they need to captur...

[AN002] Running subcycle average models on Speedgoat Performance System.

Materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) are making our power electronics converters faster and faster. This means small inductors and capacitors that make, in most cases, the cost of the devices decrease. This also means that the control devices also have to be faster, and n...



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Do you need help with your project? Need a training? email me to info @ the domain you are. Also you can book a meeting here.

¿Estás en medio de un proyecto con FPGA/SOC? ¿Necesitas formación en FPGA/SOC? Contáctame en info @ el dominio en el que estás. También puedes concertar una reunión aquí.

Copyright Pablo Trujillo 2025.