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The Gate Array News 2025.

It’s July again, and a new season is coming to an end. During this period, we’ve explored a range of topics on the blog: from how to implement electrical models on FPGAs—even on very small ones—to optimizing Speedgoat models using the fixed-point solver.

Published by P.Trujillo on Jul 27, 2025

True random number generators based on FPGA

In cybersecurity, random numbers are extremely important, and the security of some cryptographic algorithms depends directly on the quality of the random numbers generated. Typically, random numbers are produced using software algorithms. However, these are not truly random—they are pseudo-rando...

Published by P.Trujillo on Jul 13, 2025

Parallelizing SHA256 calculation on FPGA

A few weeks ago, I wrote an article where I developed a hash calculator on an FPGA. Specifically, I implemented an SHA-256 calculator. This module computes the hash of a string (up to 25 bytes) in 68 clock cycles. The design leverages the parallelism of FPGAs to compute the W matrix and the recu...

Published by P.Trujillo on Jun 29, 2025

Streaming data to DDR memory from PL on Arty board.

In the last article, we talked about using the AXI Datamover IP, which allows us to perform DDR memory transactions in a way very similar to how we would with an SoC and AXI DMA. The article used the YPCB-00388-1P1 board to transfer data from PCIe to DDR memory. This setup introduces two differe...

Published by P.Trujillo on Jun 15, 2025

Streaming data to DDR memory from PL. HW design.

We are living in a kind of data fever. Today, certain types of data are even more valuable than gold. And just like gold, data must be transported from its origin to the place where it will be used. We can extrapolate this to computing, where data is collected in bytes and must then be processed,...

Published by P.Trujillo on Jun 1, 2025

Getting started with the Ebay's Kintex7 Accelerator

To be honest, this week I had prepared another article about the carrier recovery algorithm. However, I received a board I bought some weeks ago on EBAY, and I was eager to try it out. The board is a PCIe FPGA accelerator based on the AMD Kintex7 XC7K480. It features almost half a million logic c...

Published by P.Trujillo on May 18, 2025

Writing Verilog code with Copilot

I have to admit that I started using AI tools like Copilot and ChatGPT a few months ago. Initially, I was resistant to the idea. However, after testing them on some projects, I was surprised, and now I frequently use them to generate auxiliary scripts. To be honest, I usually ask the AI to genera...

Published by P.Trujillo on May 4, 2025

Application Notes

[AN001] Designing from zero an IIR filter in Verilog using biquad structure and bilinear discretization.

Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter it they are developing for an STM32, or TI DSP or, of course, en FPGA. Filtering is such important because the majority of the applications are connected to the real world, so they need to captur...

[AN002] Running subcycle average models on Speedgoat Performance System.

Materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) are making our power electronics converters faster and faster. This means small inductors and capacitors that make, in most cases, the cost of the devices decrease. This also means that the control devices also have to be faster, and n...