%% Model sampling time 
Ts = 1e-6;

%% Model variables
L = 10e-6;
RL = 1e-3;
C = 200e-6;
Vdc = 100;
R_load = 2;


%% Gain configuration

max_dac_voltage = 10;
adc_width = 16;

% Current
max_current = Vdc/R_load * 2;
current_gain = max_dac_voltage / max_current;
current_gain_adc = current_gain / max_dac_voltage * (2^(adc_width-1)-1)

% Voltage
max_output_voltage = Vdc;
voltage_gain = max_dac_voltage / max_output_voltage;
voltage_gain_adc = voltage_gain / max_dac_voltage * (2^(adc_width-1)-1)


open_system('buck_model');
set_param(['buck_model/FPGA/Buck/Solver Configuration'],'DoFixedCost','on')

% Set number of solver iterations
set_param('buck_model/FPGA/Buck/Solver Configuration','MaxNonlinIter','2')

% Launch SS HDL advisor
sschdladvisor('buck_model')

%% Set Vivado version
hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','/media/pablo/data_m2/xilinx/Vivado/2022.1/bin/vivado');

open_system('./sschdl/buck_model/gmStateSpaceHDL_buck_model');
set_param('gmStateSpaceHDL_buck_model', 'SimulationCommand', 'Update')

hdlsetup('gmStateSpaceHDL_buck_model')

%% Set to single the model data types
set_param('gmStateSpaceHDL_buck_model/FPGA/Signal Specification','OutDataTypeStr','single');
set_param('gmStateSpaceHDL_buck_model/FPGA/Signal Specification1','OutDataTypeStr','single');
set_param('gmStateSpaceHDL_buck_model/FPGA/Signal Specification2','OutDataTypeStr','single');
set_param('gmStateSpaceHDL_buck_model/FPGA/Signal Specification3','OutDataTypeStr','single');

%% Configure and launch HDL Workflow Advisor
generate_hdlworkflow;

hdlset_param('gmStateSpaceHDL_buck_model', 'Oversampling', 100);

hdlset_param('gmStateSpaceHDL_buck_model', 'ReferenceDesignParameter', {'PCIe_Link_Width','X4','timingSeverity','warning','RearPlugin','-21','AuroraMode','None','AuroraCrc','true','AuroraByteswap','true','HDLVerifierAXI','off'});

% Set Inport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/Input voltage', 'IOInterface', 'PCIe Interface');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/Input voltage', 'IOInterfaceMapping', 'x"100"');

% Set Inport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/PWM', 'IOInterface', 'TTL IO3xx-21 [0:55]');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/PWM', 'IOInterfaceMapping', '[0]');

% Set SubSystem HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/Buck/HDL Subsystem/HDL Algorithm/State Update/Multiply State', 'SharingFactor', 1);

% Set Outport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC I output Vis', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC I output Vis', 'IOInterfaceMapping', 'Channel 01');

% Set Outport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC V output Vis', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC V output Vis', 'IOInterfaceMapping', 'Channel 02');

% Set Outport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC Trigger', 'IOInterface', 'IO334 AO Trigger [0:1]');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC Trigger', 'IOInterfaceMapping', 'Channel 01 to 08');

% Set Outport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC I output Control', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC I output Control', 'IOInterfaceMapping', 'Channel 05');

% Set Outport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC V output Control', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/DAC V output Control', 'IOInterfaceMapping', 'Channel 06');

% Set Outport HDL parameters
hdlset_param('gmStateSpaceHDL_buck_model/FPGA/PCIe Data', 'IOInterface', 'PCIe Interface');